双目OV5640摄像头

双目模块的安装

按照如下方式将双目模块插入到开发板上，注意箭头位置需要对齐。另外将P2使用跳线帽跳至+3.3V位置，使得双目模块的供电电源为3.3V。

新建vivado工程

我们要实现的结果是将双目摄像头在HDMI和LCD上实时显示出来，实现思路是用2个只写的VDMA将摄像头数据搬移到DDR中，然后再用两个只读的VDMA分别从DDR中取出然后分别通过v_axi4s_vid_out_0 IP核和v_axi4s_vid_out_1 IP核在HDMI和LCD显示。本次测试因为涉及到HDMI和LCD，所以需要参考部分之前HDMI和LVGL测试的工程代码。

在之前HDMI工程的基础上进行修改：首先使能 EMIO 的两个引脚，用来连接摄像头的 SCCB 接口，并配置的管脚约束如下：

#cam_scl:
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[9]}]
#cam_sda:
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[10]}]
#pull up
set_property PULLUP true [get_ports {emio_sccb_tri_io[9]}]
set_property PULLUP true [get_ports {emio_sccb_tri_io[10]}]

将zynq IP核的三个FCLK时钟修改成100，125，200。其中FCLK_CLK2作为扩展的ENET1的时钟。

搜索vdma进行添加：

对四个vdma进行配置，两个读，两个写，并按照下图进行参数的配置

两个只读的VDMA：

两个只写的VDMA配置：

添加两个clk_wiz IP核，一个用来驱动HDMI显示时钟，一个用来驱动LCD显示时钟，搜索clk:

设置HDMI的clk_wiz IP:将其设置为动态时钟，时钟由AXI总线进行控制，输入是通过FCLK_CLK0的100MHZ提供：

HDMI需要用到两个时钟，这两个时钟呈5倍关系：

设置LCD的clk_wiz IP:将其设置为动态时钟，时钟由AXI总线进行控制，输入是通过FCLK_CLK0的100MHZ提供：

LCD只需使能一个时钟输出：

参考之前的 HDMI Test 文档进行为HDMI显示添加其他所需要的 IP 核：

添加搜索timing核并按下图进行配置：

搜索video out核并按下图进行配置：

需要使用到自定义IP：dvi_transmitter。该 IP 核位于工程目录下的 ip_repo 文件夹中。我们需要将其添加到工程的 IP 库中。在 Block Design 中连接 DVI Transmitter 模块的接口信号，并引出外部端口（只需要引出 TMDS 端口），具体的连接方式如下图所示：

和上述步骤一样，找到我们自定义的 IP 核 ov5640_capture，将其添加到工程的 IP 库中

搜索 v_vid_in_axi4s，这个模块的作用是将标准的视频格式输出转换成AXI4-Stream 的数据流，并进行配置：

按照下图所示连接ov5640，v_vid_in_axi4s，读操作的vdma：

参考LVGL测试文档增加video out 模块，这个模块的作用是将AXI4-Stream 的数据流转换成标准的视频格式输出，与RGB LCD屏幕对应。

增加Video Timing Controller 模块：搜索并添加 video timing controller模块，并双击打开配置页进行配置：

添加一个constant模块来添加一个常量1，用于连接我们各个模块的ce以及aclken 使能

后续连接参考LVGL测试文档，至此，点击 Run connection automation 来自动连接剩下的走线，在弹出的设置对话框里勾选所有内容之后系统将自动帮我们连接好剩下的信号线以及添加需要的模块。最后生成的整体框图如下：

保存工程，然后点击source→Design Source ，右键我们创建的BLOCK工程，点击create HDL wrapper，打包BLOCK文件，至此，Block Design 部分已经设置完成。

根据原理图进行管脚配置：配置完成的.xdc：

​x
#----------------------摄像头接口的时钟---------------------------
#75M
create_clock -period 13.333 -name camera_pclk [get_ports camera_pclk_0]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets camera_pclk_0_IBUF]

create_clock -period 13.333 -name camera_pclk [get_ports camera_pclk_1]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets camera_pclk_1_IBUF]



#----------------------摄像头接口1---------------------------
set_property -dict {PACKAGE_PIN U14  IOSTANDARD LVCMOS33} [get_ports camera_rstn_0]
set_property -dict {PACKAGE_PIN U15  IOSTANDARD LVCMOS33} [get_ports camera_pwdn_0]
set_property -dict {PACKAGE_PIN U10  IOSTANDARD LVCMOS33} [get_ports {camera_data_0[0]}]
set_property -dict {PACKAGE_PIN Y11  IOSTANDARD LVCMOS33} [get_ports {camera_data_0[1]}]
set_property -dict {PACKAGE_PIN W11  IOSTANDARD LVCMOS33} [get_ports {camera_data_0[2]}]
set_property -dict {PACKAGE_PIN U7   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[3]}]
set_property -dict {PACKAGE_PIN V7   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[4]}]
set_property -dict {PACKAGE_PIN W6   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[5]}]
set_property -dict {PACKAGE_PIN V6   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[6]}]
set_property -dict {PACKAGE_PIN U5   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[7]}]
set_property -dict {PACKAGE_PIN W13  IOSTANDARD LVCMOS33} [get_ports camera_href_0]
set_property -dict {PACKAGE_PIN T9   IOSTANDARD LVCMOS33} [get_ports camera_pclk_0]
set_property -dict {PACKAGE_PIN V12  IOSTANDARD LVCMOS33} [get_ports camera_vsync_0]
#cam_scl:
set_property -dict {PACKAGE_PIN T11  IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[7]}]
#cam_sda:
set_property -dict {PACKAGE_PIN T10  IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[8]}]
#pull up
set_property PULLUP true [get_ports {GPIO_0_0_tri_io[7]}]
set_property PULLUP true [get_ports {GPIO_0_0_tri_io[8]}]


#----------------------摄像头接口2---------------------------
set_property -dict {PACKAGE_PIN Y6  IOSTANDARD LVCMOS33} [get_ports camera_rstn_1]
set_property -dict {PACKAGE_PIN Y8  IOSTANDARD LVCMOS33} [get_ports camera_pwdn_1]
set_property -dict {PACKAGE_PIN T5  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[0]}]
set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {camera_data_1[1]}]
set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {camera_data_1[2]}]
set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33} [get_ports {camera_data_1[3]}]
set_property -dict {PACKAGE_PIN W9  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[4]}]
set_property -dict {PACKAGE_PIN U9  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[5]}]
set_property -dict {PACKAGE_PIN U8  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[6]}]
set_property -dict {PACKAGE_PIN W8  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[7]}]
set_property -dict {PACKAGE_PIN V8  IOSTANDARD LVCMOS33} [get_ports camera_href_1]
set_property -dict {PACKAGE_PIN Y7  IOSTANDARD LVCMOS33} [get_ports camera_pclk_1]
set_property -dict {PACKAGE_PIN Y9  IOSTANDARD LVCMOS33} [get_ports camera_vsync_1]
#cam_scl:
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[9]}]
#cam_sda:
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[10]}]
#pull up
set_property PULLUP true [get_ports {emio_sccb_tri_io[9]}]
set_property PULLUP true [get_ports {emio_sccb_tri_io[10]}]

# beep
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[11]}]
set_property PACKAGE_PIN K18 [get_ports {GPIO_0_0_tri_io[11]}]

# PL_KEY0
set_property PACKAGE_PIN M14 [get_ports {GPIO_0_0_tri_io[0]}]
# PL_KEY1
set_property PACKAGE_PIN M15 [get_ports {GPIO_0_0_tri_io[1]}]
# PL_LED0
set_property PACKAGE_PIN N15 [get_ports {GPIO_0_0_tri_io[2]}]
# PL_LED1
set_property PACKAGE_PIN N16 [get_ports {GPIO_0_0_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[0]}]



set_property PACKAGE_PIN G14 [get_ports CAN_0_0_rx]
set_property PACKAGE_PIN J15 [get_ports CAN_0_0_tx]
set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_0_rx]
set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_0_tx]



#set_property IOSTANDARD LVCMOS33 [get_ports reset_rtl_0]
set_property PACKAGE_PIN M19 [get_ports {TMDS_0_tmds_data_p[2]}]
set_property PACKAGE_PIN G19 [get_ports {TMDS_0_tmds_data_p[1]}]
set_property PACKAGE_PIN J20 [get_ports {TMDS_0_tmds_data_p[0]}]
set_property PACKAGE_PIN L16 [get_ports TMDS_0_tmds_clk_p]
#set_property PACKAGE_PIN F16 [get_ports reset_rtl_0]


set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_sda_io]
set_property PACKAGE_PIN L14 [get_ports IIC_0_0_sda_io]
set_property PACKAGE_PIN L15 [get_ports IIC_0_0_scl_io]

set_property PACKAGE_PIN F19 [get_ports MDIO_PHY_0_mdc]
set_property PACKAGE_PIN F20 [get_ports MDIO_PHY_0_mdio_io]
set_property IOSTANDARD LVCMOS33 [get_ports MDIO_PHY_0_mdc]
set_property IOSTANDARD LVCMOS33 [get_ports MDIO_PHY_0_mdio_io]
set_property PACKAGE_PIN E18 [get_ports {RGMII_0_rd[0]}]
set_property PACKAGE_PIN E19 [get_ports {RGMII_0_rd[1]}]
set_property PACKAGE_PIN D18 [get_ports {RGMII_0_rd[2]}]
set_property PACKAGE_PIN E17 [get_ports {RGMII_0_rd[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_rx_ctl]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_rxc]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_tx_ctl]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_txc]
set_property PACKAGE_PIN A20 [get_ports {RGMII_0_td[0]}]
set_property PACKAGE_PIN B20 [get_ports {RGMII_0_td[1]}]
set_property PACKAGE_PIN C20 [get_ports {RGMII_0_td[2]}]
set_property PACKAGE_PIN D19 [get_ports {RGMII_0_td[3]}]
set_property PACKAGE_PIN H17 [get_ports RGMII_0_rx_ctl]
set_property PACKAGE_PIN H16 [get_ports RGMII_0_rxc]
set_property PACKAGE_PIN D20 [get_ports RGMII_0_tx_ctl]
set_property PACKAGE_PIN B19 [get_ports RGMII_0_txc]

set_property SLEW FAST [get_ports {RGMII_0_td[0]}]
set_property SLEW FAST [get_ports {RGMII_0_td[1]}]
set_property SLEW FAST [get_ports {RGMII_0_td[2]}]
set_property SLEW FAST [get_ports {RGMII_0_td[3]}]
set_property SLEW FAST [get_ports RGMII_0_tx_ctl]
set_property SLEW FAST [get_ports RGMII_0_txc]

create_clock -period 8.000 -name RGMII_0_rxc -waveform {0.000 4.000} [get_ports RGMII_0_rxc]
#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {gmii_clk_25m_out gmii_clk_2_5m_out}] -group [get_clocks -include_generated_clocks gmii_clk_125m_out]

set_property PACKAGE_PIN K14 [get_ports UART_1_0_txd]
set_property PACKAGE_PIN J14 [get_ports UART_1_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_0_txd]

set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_sda_io]
set_property PACKAGE_PIN U13 [get_ports IIC_1_0_sda_io]
set_property PACKAGE_PIN V16 [get_ports IIC_1_0_scl_io]

set_property PACKAGE_PIN V18 [get_ports lcd_de]
set_property PACKAGE_PIN W18 [get_ports lcd_hsync]
set_property PACKAGE_PIN W19 [get_ports lcd_vsync]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_de]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_hsync]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_vsync]

# R
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[16]}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {lcd_data[17]}]
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {lcd_data[18]}]
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[19]}]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {lcd_data[20]}]
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {lcd_data[21]}]
set_property -dict {PACKAGE_PIN U18  IOSTANDARD LVCMOS33} [get_ports {lcd_data[22]}]
set_property -dict {PACKAGE_PIN U19  IOSTANDARD LVCMOS33} [get_ports {lcd_data[23]}]
# G
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports {lcd_data[8]}]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {lcd_data[9]}]
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {lcd_data[10]}]
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {lcd_data[11]}]
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[12]}]
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {lcd_data[13]}]
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {lcd_data[14]}]
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {lcd_data[15]}]
# B
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {lcd_data[0]}]
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[1]}]
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {lcd_data[2]}]
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {lcd_data[3]}]
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[4]}]
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports {lcd_data[5]}]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {lcd_data[6]}]
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports {lcd_data[7]}]


set_property IOSTANDARD LVCMOS33 [get_ports {lcd_reset[0]}]
set_property PACKAGE_PIN P20 [get_ports {lcd_reset[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_clk]
set_property PACKAGE_PIN W14 [get_ports lcd_clk]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[4]}]
# lcd_bl
set_property PACKAGE_PIN V17 [get_ports {GPIO_0_0_tri_io[4]}]
# lcd_tp_reset
set_property PACKAGE_PIN V13 [get_ports {GPIO_0_0_tri_io[5]}]
# lcd_tp_int
set_property PACKAGE_PIN N20 [get_ports {GPIO_0_0_tri_io[6]}]

对工程进行编译和综合,生成bitstream,File→Export→Export hardware，导出.xsa文件。

新建vitis工程

同样新建平台工程和应用工程，此次新建的代码文件是在18-LVGL文档和19-AUDIO代码的基础上进行修改：添加新的摄像头相关的文件代码：新建文件夹emio_sccb_cfg，ov5640，新建文件xadc.c，最终需要的src文件如下：

修改clk_wiz文件代码：

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//clk_wiz.c
#define CLK_CFG3_OFFSET  0x20c
bool clk_wiz_cfg(uint32_t clk_device_id, double freq_MHz, double freq2_MHz)
{
    double div_factor = 0;
    uint32_t div_factor_int = 0, div_factor_frac = 0;
    uint32_t clk_divide = 0;
    uint32_t status = 0;

    // init XCLK_Wiz
    XClk_Wiz_Config *clk_cfg_ptr;
    clk_cfg_ptr = XClk_Wiz_LookupConfig(clk_device_id);
    XClk_Wiz_CfgInitialize(&clk_wiz_inst, clk_cfg_ptr, clk_cfg_ptr->BaseAddr);

    if (freq_MHz <= 0) return false;
    // config to 10X
    XClk_Wiz_WriteReg(clk_cfg_ptr->BaseAddr, CLK_CFG0_OFFSET, 0x00000a01);

    // ===== config clockout1 =====
    div_factor = CLK_WIZ_IN_FREQ * 10 / freq_MHz;
    div_factor_int = (uint32_t)div_factor;
    div_factor_frac = (uint32_t)((div_factor - div_factor_int) * 1000);
    clk_divide = div_factor_int | (div_factor_frac << 8);
    XClk_Wiz_WriteReg(clk_cfg_ptr->BaseAddr, CLK_CFG2_OFFSET, clk_divide);

    // ===== config clockout2 =====
    if (freq2_MHz > 0)
    {
        double div_factor2 = CLK_WIZ_IN_FREQ * 10 / freq2_MHz;
        uint32_t div_factor2_int = (uint32_t)div_factor2;
        uint32_t div_factor2_frac = (uint32_t)((div_factor2 - div_factor2_int) * 1000);
        uint32_t clk_divide2 = div_factor2_int | (div_factor2_frac << 8);
        XClk_Wiz_WriteReg(clk_cfg_ptr->BaseAddr, CLK_CFG3_OFFSET, clk_divide2);
    }

    // update
    XClk_Wiz_WriteReg(clk_cfg_ptr->BaseAddr, CLK_CFG23_OFFSET, 0x00000003);

    // wait for lock
    while (1)
    {
        status = XClk_Wiz_ReadReg(clk_cfg_ptr->BaseAddr, CLK_SR_OFFSET);
        if (status & 0x00000001) // Bit0 Locked
            return true;

        usleep(1000);
    }

    return false;
}

main.c：

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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "xil_types.h"
#include "xil_cache.h"
#include "xparameters.h"
#include "xaxivdma.h"
#include "xaxivdma_i.h"
#include "display_ctrl_hdmi/display_ctrl_hdmi.h"
#include "vdma_api/vdma_api.h"
#include "emio_sccb_cfg/emio_sccb_cfg.h"
#include "ov5640/ov5640_init.h"

#define CAM0_VDMA_ID        XPAR_AXIVDMA_2_DEVICE_ID    // camera0 VDMA device ID
#define CAM1_VDMA_ID        XPAR_AXIVDMA_3_DEVICE_ID    // camera1 VDMA device ID
#define HDMI_VDMA_ID        XPAR_AXIVDMA_0_DEVICE_ID    // HDMI VDMA device ID
#define LCD_VDMA_ID         XPAR_AXIVDMA_1_DEVICE_ID    // LCD VDMA device ID
#define HDMI_VTC_ID         XPAR_VTC_0_DEVICE_ID        // HDMI VTC device ID
#define LCD_VTC_ID          XPAR_VTC_1_DEVICE_ID        // LCD VTC device ID
#define HDMI_CLK_WIZ_ID     XPAR_CLK_WIZ_0_DEVICE_ID    // HDMI clock wiz device ID
#define LCD_CLK_WIZ_ID      XPAR_CLK_WIZ_1_DEVICE_ID    // LCD clock wiz device ID

#define BYTES_PIXEL        3                           // RGB888 => 3bytes

//frame buffer address
unsigned int const cam0_frame_buffer_addr = (XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x1000000);
unsigned int const disp_frame_buffer_addr = cam0_frame_buffer_addr;
unsigned int cam1_frame_buffer_addr;


XAxiVdma     cam0_vdma;
XAxiVdma     cam1_vdma;
XAxiVdma     hdmi_vdma;
XAxiVdma     lcd_vdma;
DisplayCtrl  hdmi_disp_ctrl;
DisplayCtrl  lcd_disp_ctrl;
// VideoMode    *vd_mode = &VMODE_1024x600;
VideoMode    *vd_mode = &VMODE_1280x720;

int main(void)
{
    u32 status0,status1;
    u16 cmos_h_pixel; 
    u16 cmos_v_pixel; 
    u16 total_h_pixel;
    u16 total_v_pixel;

    if (vd_mode == &VMODE_800x480)
    {
        total_h_pixel = 1800;
        total_v_pixel = 600;
    }
    else if (vd_mode == &VMODE_1024x600)
    {
        total_h_pixel = 2200;
        total_v_pixel = 1000;
    }
    else if (vd_mode == &VMODE_1280x720)
    {
        total_h_pixel = 2570;
        total_v_pixel = 980;
    }

    Xil_DCacheDisable();

    cam1_frame_buffer_addr = cam0_frame_buffer_addr + vd_mode->width * BYTES_PIXEL/2;

    emio_init();
    status0 = ov5640_init(CAM0_CH0,vd_mode->width/2,
                        vd_mode->height,
                        total_h_pixel,
                        total_v_pixel);

    status1 = ov5640_init(CAM1_CH1,vd_mode->width/2,
                        vd_mode->height,
                        total_h_pixel,
                        total_v_pixel);

    if(status0 == 0 && status1 == 0)
        xil_printf("Dual OV5640 detected successful!\r\n");
    else
        xil_printf("Dual OV5640 detected failed!\r\n");

    //CAM0 VDMA
    run_vdma_frame_buffer(&cam0_vdma, CAM0_VDMA_ID, vd_mode->width, vd_mode->height,
                            cam0_frame_buffer_addr,0,0,ONLY_WRITE);
    //CAM1 VDMA
    run_vdma_frame_buffer(&cam1_vdma, CAM1_VDMA_ID, vd_mode->width, vd_mode->height,
                            cam1_frame_buffer_addr,0,0,ONLY_WRITE);

    //HDMI
    run_vdma_frame_buffer(&hdmi_vdma, HDMI_VDMA_ID, vd_mode->width, vd_mode->height,
                            disp_frame_buffer_addr,0,0,ONLY_READ);
    clk_wiz_cfg(HDMI_CLK_WIZ_ID, vd_mode->freq, vd_mode->freq2);
    DisplayInitialize(&hdmi_disp_ctrl, HDMI_VTC_ID);
    DisplaySetMode(&hdmi_disp_ctrl, vd_mode);
    DisplayStart(&hdmi_disp_ctrl);

    // //LCD
    // run_vdma_frame_buffer(&lcd_vdma, LCD_VDMA_ID, vd_mode->width, vd_mode->height,
    //                         disp_frame_buffer_addr,0,0,ONLY_READ);

    // clk_wiz_cfg(LCD_CLK_WIZ_ID, vd_mode->freq);
    // DisplayInitialize(&lcd_disp_ctrl, LCD_VTC_ID);
    // DisplaySetMode(&lcd_disp_ctrl, vd_mode);
    // DisplayStart(&lcd_disp_ctrl);

    while(1)
    {
    }
    
    return 0;
}

编译调试

将HDMI，LCD和ZYNQ开发板进行连接，

使用TYPE-C连接开发板JTAG口和电脑，进行Build,debug，观察HDMI或LCD显示。